Memory devices (such as flash memories) are commonly used to store data. Typically, a memory device includes a matrix of memory cells (for example, consisting of floating-gate MOS transistors with a programmable threshold voltage). During a reading operation, selected memory cells are suitably biased so that a current sunk by each memory cell (flowing through a corresponding bitline) will be indicative of its threshold voltage (and then of the logic value stored therein).
The reading of each memory cell is generally implemented by means of a sense amplifier; the sense amplifier correctly biases the memory cell and then compares the corresponding current with another current provided by a reference cell. In the solutions known in the art, the sense amplifier is based on a current-to-voltage converter (typically consisting of a pair of transistors in current-mirror configuration); this element converts the cell current and the reference current into corresponding voltages, which are then fed to a comparator. Preferably, each branch of the current mirror includes a biasing circuit, which is formed by a cascode transistor with an inverter in feedback configuration. This biasing circuit speeds-up the charging of stray capacitances intrinsically associated with the bitline, then reducing a transient phase of the reading operation; moreover, it decouples the current mirror from this high capacitive load (thereby improving its performance). Accordingly, the time required for accessing the data stored in the memory device is greatly reduced.
Nowadays, many memory devices are designed to work with low-power supply voltages (for example, down to 1.2-1.8 V). The use of low-power supply voltages allows exploiting technologies based on very thin gate oxide layers; therefore, it is possible to implement memory devices that are more compact and exhibit lower power consumption.
Nevertheless, it is preferred not to scale down the voltage that is used to bias the memory cell during the reading operation (in order to keep the current sunk by the memory cell relatively high). In fact, a reduction of the cell current would increase the discharge time of the corresponding bitline. This has a negative impact on the access time of the memory device; the problem is particular acute in fast logic circuits, such as microprocessors, DSPs, peripherals and the like. Optimal values of the biasing voltage (which do not affect operation of the memory device) are about 0.8-0.9 V.
Therefore, a measure voltage (which is provided to the comparator by the branch of the current mirror associated with the memory cell) has a swing that is restrained between the biasing voltage that has to be applied to the memory cell (0.8-0.9V) and the supply voltage that is available for operating the current mirror (down to 1.2 V). This reduced swing of the measure voltage impairs the accuracy of the sense amplifier (since it hinders the discrimination of the different logic values stored in the memory cell). Moreover, in the worst-case working conditions of the memory device the supply voltage may also fall towards lower values (down to 0.9-1 V); in this case, the correct operation of the sense amplifier cannot be guaranteed.
A solution to the problem is described in US Patent Publication No. 2104/0160837. In this case, the current mirror is connected in parallel to the bitline. The bitline is then biased by a circuit including a MOS transistor that is cascode-connected to an operational amplifier; the operational amplifier receives a reference voltage and the bitline voltage, and then controls the MOS transistor accordingly. However, this architecture increases the access time (with respect to the solutions based on the inverter); moreover, the converter is now forced to operate below the bitline voltage.
Alternative solutions exploit charge pumps for supplying voltages bootstrapped with respect to the supply voltage to the sense amplifier. However, these solutions involve higher power consumption and introduce noise problems.